Demands for increased performance and complexity for integrated circuits have led to the circuits including both CMOS transistors for high packing density and bipolar transistors for high power and speed. Such BiCMOS circuits provide particular advantages for mixed mode (analog plus digital) integrated circuits which can combine the low noise characteristics of bipolar transistors in analog subcircuits and still use well known CMOS digital subcircuits. See for example, R. Haken et al, "BiCMOS Processes for Digital and Analog Devices," Semiconductor International 96 (June 1989).
However, analog circuits typically will operate with both positive and negative power supplies and at higher voltages than the single power supply digital circuit. For example, digital CMOS circuits typically operate between 0 and +5 volts, whereas analog circuits may operate with -5 volts, +5 volts. Further, analog circuits benefit from the use of CMOS transistors in addition to bipolar transistors; thus a mixed mode BiCMOS circuit may have CMOS transistors operating between 0 and +5 volts plus other CMOS transistors operating between -5 and +5 volts. But to achieve maximum performance from the digital (low voltage) NMOS transistors the source and drain implant doses are maximized to the extent where hot electron failures begin to appear. And using the same source and drain implant doses for the analog (high voltage) NMOS transistors will result in failure due to the higher operating voltages of the analog transistors. Thus there is a problem of a tradeoff between digital NMOS transistor performance and analog NMOS transistor performance in BiCMOS integrated circuits.
In BiCMOS processes the photomask count is typically high, and increasing the number of photomasks to obtain additional devices is only used as a last resort. Thus for a BiCMOS process which provides both NPN and PNP transistors, the implant to form the base of the PNP transistors seems to be a candidate for simultaneous formation of the source and drain (or just drain in the asymmetrical case) of the high voltage NMOS transistors because the implant dose for base is most similar to that used in a lightly doped drain of a high voltage NMOS transistor. However, to achieve a PNP transistor of reasonable performance, the base implant must be of fairly high energy to provide a satisfactory base width due to the encroachment of the faster diffusing boron dopants forming the P+emitter. But if upwards of 1 MeV energy for the base implant is not available, then a higher dose must be used. Then the high voltage NMOS transistor becomes prone to hot electron degradation as well as low snapback holding voltage.
The present invention provides BiCMOS processes and devices with low voltage and high voltage NMOS transistors having differing drain (and source) dopings but without an additional photomask. Rather, the high voltage NMOS transistors have a compensated lightly doped drain formed by use of both the NPN transistor base implant and the PNP transistor base implant. Because a boron implant can be deeper and diffuse more quickly, it is generally true that the NPN base implant dose will be less than but of the same order of magnitude as the PNP base implant dose. The combination of the two base implants yields a drain (and source) which is N type and more lightly doped than the PNP base alone. Hence, such high voltage NMOS transistors should have greater hot electron immunity and snapback holding voltage. Ohmic contact to the lightly doped drain (and source) may be by use of the low voltage NMOS transistor source/drain implant or the NPN transistor emitter implant and offset from the high voltage NMOS transistor gate.